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Floating Point Adder with Pipelining Using VHDL
Abstract— Floating Point arithmetic is by far the most used way of approximating real number arithmetic for performing numerical calculations on modern computers. Each computer had a different arithmetic for long time: bases, significant and exponents’ sizes, formats, etc. Each company implemented its own model and it hindered the portability between different equipments until IEEE 754 standard appeared defining a single and universal standard. The aim of this project is implementing a floating point adder with pipelining according with the IEEE 754 standard and using the hardware programming language VHDL, which results in reduced processing time, reduced system delay, increased efficiency with accuracy.
Index Terms—Floating point adder, VHDL ,Pipelining technique, Adder
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International Journal for Trends in Technology & Engineering © 2015 IJTET JOURNAL