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Design Of DSP Application In Low Power Specific Parallel Array Multiplier
Abstract- A digital signal processor is an important kernel of multiplier. Two important design of multiplier factor is Power consumption and area owing to circuit complexity. For each portable device the power consumption issue of avoiding cooling package and reliability issues is simply too difficult for massive battery life and high finish circuits. Selective activation multiplier and partitioned multiplier have a two architectures can be proposed for a two-input signed multipliers are decreased by power consumption. The multiplier of area and speed is important for speed increment which results for large area consumption. It ought to be fast and consume less space by multiplying. Average the area and time overhead by prior-art low-power techniques may be easily implemented.
Index Terms— Discrete wavelet transforms, Discrete cosine transform, Information entropy, Low-pass Filters Multiplying circuits, Power dissipation, Partitioned multiplier, Selective activation multiplier
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International Journal for Trends in Technology & Engineering © 2015 IJTET JOURNAL