An Efficient Design of Low power Baugh Wooley Multiplier with Carry Save Adder for DSP Applications
Abstract- In this paper we have proposed Baugh Wooley Multiplier with carry skip adder. Baugh Wooley multiplier performs an multiplication operation on signed numbers only. Most signal processing application performs truncated multiplication in order to decrease the word size. When direct truncation is used it provides significant savings in power, area, complexity and timing it can also introduces large amount of error in the output. so here in this paper a programmable truncated Baugh Woolley multiplier to enhance the speed and to reduce the critical path delay. The proposed work designed on 8 bit and 16 bit and study also shows the comparison between carry save adder and redesigned the carry skip adder using Baugh Woolley multiplier having reduced area, power and delay. The Carry Save Adder (CSA) tree and the Carry skip (CSA) adder used to reduce the power consumption compared to conventional one multiplier operation. Since signed multiplication operation is performed by the same multiplier unit and the area reduces the multiplier complexity and also less power and which is analyzed in in Xilinx ISE 14.2 i.
Index Terms— Digital signal processing (DSP), fault tolerant, low power, carry save adder, carry skip adder, truncatedmultiplication.
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