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Design and analysis of low power pulse triggered flip-flops and its implementation
Abstract -Low Power analysis is a major concern in today’s VLSI world. Much, continuance system like flip-flop (FF) consumes giant portion of total chip power. Thus during this paper we tend to discuss concerning style the planning the look} of the clock system exploitation novel Flip-Flop design. During this paper, a unique low-power pulse-triggered flip-flop (FF) style is bestowed. Pulse- triggered FF (P-FF) has been thought-about as a well-liked different to the traditional master –slave primarily based F. a low-power flip-flop (FF) style that includes a particular kind pulse-triggered structure and a changed true single section clock latch supported a symbol feed-through theme is bestowed. The planned style with success solves the long discharging path drawback in standard express kind pulse-triggered FF (P-FF) styles and achieves higher speed and power performance within the applications of high speed. These circuits are simulated exploitation Tanner Tools with 90nm technology.
Index Terms—Clocking System, Power Dissipation, Pulse-triggered flip-flop (FF), and True single phase clock latch.
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International Journal for Trends in Technology & Engineering © 2015 IJTET JOURNAL