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Design and analysis of low power full adders using adiabatic logic
Abstract - Power consumption and delay are two important considerations for VLSI systems. Our prime motive is to reduce the power and to get less delay that is nothing but the high speed for any design. So adder is one of the fundamental blocks present in arithmetic logic unit (ALU), floating point unit. Adders are very important components in some other applications such as microprocessor and digital signal processing (DSP) architectures. Digital signal processors and Microprocessors mainly rely on highly efficient implementations of generic floating point units and arithmetic logic units. In this paper complementary pass transistor logic presented and it will used to design a full adder circuit using XOR-XNOR design. And validate and compare the parameters to the other logic styles. The proposed full adder circuit are based on 3T based XNOR-XOR gates which could be highly reduced the power and delay. For further reducing the power and delay we are going to propose the adiabatic logic (EEAL and ECRL) based full adders.This circuit has been designed and verified by using TANNER EDA tools.
Index Terms—Adiabatic logic, Dynamic dissipation, ECRL and EEAL, Full adder, Recycling, XOR-XNOR.
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International Journal for Trends in Technology & Engineering © 2015 IJTET JOURNAL