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Novel SEC-DAEC-DNAEC Correction Codes Derived From Orthogonal Latin Square Codes
Abstract— Memories are more prone to errors. Redundancy is one technique to get rid of the errors in memories ie, to add some extra data to a message, which the receiver can use to check correctness of the data at the receiver side, and to get the data that is said to be corrupt. In order to ensure that memory contents are error free, single error correction double error detection (SEC-DED) codes are used, however, with recent advancement in technology, soft errors often affect more than one memory bit. But SEC-DED codes will not be able to correct multiple errors, and so interleaving is one common method that has been adopted. Interleaving has always affected memory design and cannot be used in memories at all circumstances. SEC-DED-DAEC codes when used has higher rates of decoder complexity and delay. Another important issue is that most of the time the methods that are carried out in new SEC-DED-DAEC codes may miscorrect some double nonadjacent bit errors. Apart from these methods OLS codes can be used, that can correct memories and caches. Their error correction capabilities can be adapted to the error rate or to the mode of operation. In this brief, a new class of SEC-DED DAEC DNAEC codes is derived from orthogonal Latin squares codes is presented. The new codes significantly reduce the decoding complexity and delay. Furthermore it has the advantage of reduced check bits and also has improved reliability of correcting even the errors that are not adjacently occurring.
Index Terms— Single Error Correction (SEC), Double Adjacent Error Correction (DAEC), Memory, Orthogonal Latin squares (OLS)
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International Journal for Trends in Technology & Engineering © 2015 IJTET JOURNAL