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Analysis of leakage current calculation for nanoscale MOSFET and FinFET
Abstract—This paper presents logic level estimators of leakage current for nanoscale digital standard cell circuits. Here the proposed estimation model is based on the characterization of internal node voltages of cells and the characterization of leakage current in a single Field-Effect Transistor (FET). Finally the estimation model allowed direct implementation of supply voltage variation impact on leakage current and output voltage drop (loading effect).The technique is feasible for implementation in Hardware Description Language (HDL) and HDL cell models supporting leakage estimation at simulation time.
Index Terms— FET, HDL, Leakage current, Standard cell
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International Journal for Trends in Technology & Engineering © 2015 IJTET JOURNAL